1. Field of the Invention
This invention relates to the field of analog circuits, and, in particular, to write circuitry for magnetic recording systems.
2. Background Art
In magnetic data recording systems, data information is recorded on a disk surface by individually modifying the magnetic orientation of small regions of the disk surface. This modification is performed by placing a strong, localized magnetic field of the desired orientation in close proximity to the selected region of the disk surface. In disk drives, the magnetic field is typically generated by a xe2x80x9cwrite headxe2x80x9d suspended from an arm over the disk surface. The write head contains an inductive coil capable of producing a localized electromagnetic field with direction and magnitude dependent on electrical current passed through the inductive coil. Data is written on the disk surface by changing current direction in the writing head. The apparatus used to direct current through the inductive coil of the write head is generally known as a xe2x80x9cwrite driver.xe2x80x9d
Typically, H-bridge configurations are used for write drivers. A symbolic diagram of an H-bridge is shown in FIG. 1A. The inductive head (LHEAD) is coupled across nodes HX and HY. Upper switches S1 and S2 couple nodes HX and HY, respectively, to the positive voltage supply (VCC). Lower switches S3 and S4 couple nodes HX and HY, respectively, to current source IW. Current source IW is further coupled to a lower voltage supply or ground (GND) node. It is also possible to orient the H-bridge such that the current source is above the upper switches rather than below the lower switches. The upper switch may consist of NPN or PNP bipolar junction transistors (BJTs), or P-type field effect transistors (PFETs). NPN BJTs or Ntype FETs are typically used for the lower switches.
The switches of the write driver are used to steer the write current provided by constant current source IW through the inductor LHEAD. To steer current through LHEAD from node HX to node HY, upper switch S1 and lower switch S4 are closed to provide a current path from VCC to GND that passes through LHEAD, while switches S2 and S3 are open circuits (as shown in FIG. 1A). To change the direction of current flow to pass from node HY to node HX, switches S2 and S3 are closed, and switches S1 and S4 are open.
FIG. 1B shows a write driver circuit implementation of the prior art. NPN transistors Q101 and Q102 correspond to upper switches S1 and S2 of FIG. 1A. Schottky transistors Q103 and Q104 correspond to lower switches S3 and S4. The collectors of transistors Q101 and Q102 are coupled to VCC. The emitters of transistors Q101 and Q102 are coupled to nodes HX and HY, respectively. Resistors R111 and R112 are coupled to VCC and to the base junctions of transistors Q101 and Q102, respectively. The collectors of Schottky transistors Q103 and Q104 are coupled to nodes HX and HY, respectively. The emitters of Schottky transistors Q103 and Q104 are coupled to constant current source IW, which is in turn coupled to ground (GND). The base junction of transistor Q103 is coupled through resistor R113 to voltage input WDX. The base junction of transistor Q104 is coupled through resistor R114 to voltage input WDY. The collectors of Schottky transistors Q105 and Q106 are coupled to the base junctions of transistors Q101 and Q102, respectively. The emitters of transistors Q105 and Q106 are coupled together to constant current source I1. The base junctions of transistors Q105 and Q106 are coupled to voltage inputs WDX and WDY, respectively. Current source I1 is further coupled to ground.
The circuit of FIG. 1B operates from the differential voltage input provided by WDX and WDY. When WDX is at a higher potential than WDY, transistors Q103 and Q105 are conducting, whereas transistors Q104 and Q106 are not conducting. Transistor Q105 pulls down the base voltage of transistor Q101, shutting off the current through transistor Q101. The base junction of transistor Q102 is pulled near VCC by resistor R112, turning on transistor Q102. The H-bridge current path consists of transistor Q102, inductor LHEAD, transistor Q103 and current source IW.
When WDY is at a higher potential than WDX, transistors Q104 and Q106 are conducting, whereas transistors Q103 and Q105 are not conducting. Transistor Q106 pulls down the base voltage of transistor Q102, shutting off the current through transistor Q102. The base junction of transistor Q101 is pulled near VCC by resistor R111, turning on transistor Q101. The H-bridge current path becomes transistor Q101, inductor LHEAD, transistor Q104 and current source IW.
The Schottky transistors can be modeled as standard NPN transistors with a Schottky diode coupled between the base and collector junctions. The Schottky diode conducts current from the base to the collector when the base-collector voltage of the transistor becomes forward biased and reaches approximately 0.3 volts, depending on the device process. This action serves to clamp the base-collector voltage to a maximum of 0.3 volts. For an active transistor with a base-emitter voltage of 0.7 volts, the collector-emitter voltage may never drop below approximately 0.4 volts. Therefore, the clamped transistor cannot go into saturation and transistor switching speed can be maintained.
Transistors Q101 and Q102 do not require Schottky clamping because, in the circuit of FIG. 1B, the base-collector voltage of these devices can never exceed zero volts without shutting off the transistor.
Since the write head is an inductor, a certain amount of induced voltage appears across the inductive load. Rise and fall transition times, xe2x80x9ctrxe2x80x9d and xe2x80x9ctfxe2x80x9d, of the head write current are given by the following equation:
tr=tf=Lh*xcex94Ih/Vh
where Lh is the head inductance, xcex94Ih is the change in current and Vh is the available voltage across the write head, also referred to as the head voltage swing. Because the rise and fall times are inversely related to the head voltage swing, a higher head voltage swing provides shorter rise and fall transition times, e.g. faster performance. Therefore, it is desirable to maximize the available head voltage swing.
The head voltage swing is determined by the voltage range between the upper and lower power supplies that is not taken up by the devices in the current path. In the circuit of FIG. 1B, the head voltage swing is set by VCC less the minimum voltage across devices Q101, Q104 and IW (or, equivalently, devices Q102, Q103 and IW). The peak head voltage swing for FIG. 1B is given by:
Vh(peak)=VCCxe2x88x92(VBE+VCE,min+VIW)
where Vh(peak) is the head voltage swing, VBE is the base-emitter voltage of the upper active transistor, VCE,min is the minimum collector-emitter voltage of the lower active transistor, and VIW is the voltage across current source IW.
One method for improving the head voltage swing in low power applications with voltage supplies at or below five volts is discussed in U.S. Pat. No. 5,386,328 granted to Chiou et al., issued Jan. 31, 1995, and assigned to the assignee of the present invention. A method and apparatus are disclosed in the ""328 patent for maximizing the head voltage swing in a limited supply voltage range such as 3.3 volts. The circuit of the ""328 patent comprises a current mirror-based write driver. A symbolic diagram of this current mirror-based write driver is shown in FIG. 2A.
In FIG. 2A, upper switches S1 and S2 are positioned relative to the head inductor as in FIG. 1A. However, Switches S3 and S4 have been relocated to a parallel current path along with the current source IW/n. Coupled between nodes HX and HY and the ground node (GND) are current mirror blocks 210 and 202, respectively. Switch S3 is coupled between current source IW/n and current mirror 201. Switch S4 is coupled between current source IW/n and current mirror 202. Current source IW/n is further coupled to VCC. The inputs of current mirror blocks 201 and 202, originating from switches S3 and S4, are labeled IX and IY.
When switch S4 is closed, the current from current source IW/n is channeled to current mirror block 202. Current mirror block 202 draws current from node HY in response to the current supplied through switch S4. The current drawn from node HY is related to the current provided by current source IW/n by the ratio of 1:n, so that the current drawn from node HY is equal to IW. Current mirror block 201 provides the same current mirroring function to node HX when switch S3 is closed. When either of switches S3 or S4 are open, no current is provided to the corresponding current mirror block, and, therefore, no current is drawn from the respective head node.
FIG. 2B is a circuit diagram of elements S1, S2, LHEAD, 201 and 202 of FIG. 2A. In FIG. 2B, upper switches S1 and S2 are implemented with P-type FET devices M211 and M212, respectively. Current mirror block 201 comprises transistors Q221, Q223 and Q225, and resistor R232. Current mirror block 202 comprises transistors Q222, Q224 and Q226, and resistor R233. Resistor R231 is shared by both current mirror blocks.
Control voltage inputs GX and GY are provided to the gates of transistors M211 and M212, respectively. The sources of transistors M211 and M212 are coupled to VCC. The drains of transistors M211 and M212 are coupled to nodes HX and HY, respectively. The collectors of Schottky transistors Q221 and Q222 are coupled to nodes HX and HY respectively. The emitters of transistors Q221 and Q222 are commonly coupled through resistor R231 to ground. The collectors of transistors Q225 and Q226 are coupled to VCC. The emitter of transistor Q225 is coupled to the base junctions of Schottky transistors Q221 and Q223. The emitter of transistor Q226 is coupled to the base junctions of Schottky transistors Q222 and Q224. Current input IX is coupled to the base junction of transistor Q225 and the collector junction of transistor Q223. Current input IY is coupled to the base junction of transistor Q226 and the collector junction of transistor Q224. The emitter junction of transistor Q223 is coupled through resistor R232 to ground. The emitter junction of transistor Q224 is coupled through resistor R233 to ground.
Current is provided through either input IX or input IY at any one time. If current is being supplied to input IX, suitable voltage signals are applied to the gates of transistors M211 and M212 such that transistor M211 presents an open circuit between node HX and VCC, and transistor M212 presents a low resistance (closed circuit) between node HY and VCC. If current is supplied to input IY, suitable voltage signals are applied to the gates of transistors M211 and M212 such that transistor M212 presents an open circuit and transistor M211 presents a low resistance path.
For current mirror block 201, comprised of transistors Q221, Q223 and Q225, operation is as follows. When current is supplied to input IX, substantially all of the current supplied is channeled through the collector and emitter of transistor Q223. The voltage at the emitter of transistor Q223 is equal to the voltage drop across resistor R232 generated by the current from input IX. Because transistors Q221 and Q223 share a common base node, and because their VBE voltage drops are substantially the same, the emitter voltage of transistor Q221 is substantially equal to the emitter voltage of transistor Q223. Therefore, the voltage drop across resistor R231 is equal to the voltage drop across resistor R232. The current through resistor R231 and transistor Q221 is then equal to the current from input IX modified by a ratio consisting of the resistance of R232 over the resistance of R231 (or R232/R231). If R232/R231 is equal to xe2x80x9cnxe2x80x9d, and the current at IX is IW/n, then the current drawn from node HX is IW. The base current of transistor Q223 and the proportionally larger base current of transistor Q221 are provided by transistor Q225. Because the current gain through transistor Q225 is relatively large (xcex2 greater than  greater than 1), the base current drawn by transistor Q225 to provide base current for transistors Q221 and Q223 is negligible compared to current input IX. When no current is supplied to input IX, transistors Q221, Q223 and Q225 are substantially non-conducting. The operation of current mirror block 202 is similar to that of current mirror block 201 described above.
The head voltage swing of the circuit of FIG. 2B is determined by the voltage drop across the upper P-type FET switch, the collector-emitter voltage of the active lower Schottky transistor (Q221 or Q222), and the voltage drop across resistor R231:
Vh(peak)=VCCxe2x88x92(VSD+VCE,min+VR231)
where VSD is the source-drain voltage of FET M211 or M212, VCE,min is the collector-emitter voltage of either transistor Q221 or Q222, and VR231 is the voltage drop across resistor R231. The peak head voltage swing in the circuit of FIG. 2B provides at least 0.7 volts more head voltage swing than the circuit of FIG. 1B, which may be significant in low power applications operating with power supplies of five volts or less.
However, the circuits of the prior art, while attempting to optimize head voltage swing inside of a set voltage supply range, have an inherent limitation in the maximum range of the power supply, and hence a design limitation on the head voltage swing available. As shown above in the head voltage swing equations for the circuits of FIGS. 1B and 2B, the head voltage swing is comprised of several substantially constant voltage components and one varying voltage component. This varying component is the collector-emitter voltage of the lower switch transistor or lower current mirror transistor (Q221 or Q222 in FIG. 2B). This collector-emitter voltage absorbs all of the voltage swing of the inductive load. The complete head voltage swing is therefore not only dependent on the minimum collector-emitter voltage of these critical transistors, but on the maximum collector-emitter voltage of these devices when in a non-conducting state, i.e., the breakdown voltage, BVCEO. If the voltage across the non-conducting lower transistor exceeds the breakdown voltage, breakdown will occur and the transistor will not remain in the desired xe2x80x9coffxe2x80x9d state.
FIG. 3A illustrates the relative waveforms of the voltage levels at nodes HX and HY during a write current reversal. The associated inductor current waveform is illustrated in FIG. 3B. In FIG. 3A, before the transition, nodes HX and HY are offset by a small voltage due to the steady state current +IW and the series resistance of the inductor. The upper voltage node is pulled near the upper voltage rail (power supply) by the closed upper switch S1. For the circuit of FIG. 1B, node HX is initially at approximately 0.7 volts below VCC in steady state with positive current flow (current flowing from node HX to node HY). For the circuit of FIG. 2B, node HX is initially very near VCC.
In the transition period, as the write current changes polarity, the head voltage switches polarity with a large spike of magnitude Vh(peak). The voltage at node HY is pulled near the upper voltage rail by newly closed upper switch S2. Node HX absorbs the majority of the induced head voltage swing Vh(peak), to the extent allowed by the circuit design, before settling into steady state. In the new steady state, node HX is slightly offset below node HY due to the negative current flowing through the inductor series resistance.
As shown above, the head voltage swing limits the transition rate of the head current waveform. Therefore, the head voltage swing must be maximized to increase the current transition rate. However, the H-bridge circuit designs of the prior art are subject to device process limitations. For instance, in a five volt process, semiconductor devices can break down (BVCEO) at as low as 5.5 volts. This proves to be a limiting factor when larger head voltage swings are required, for instance, when VCC is raised from five volts to twelve volts. A weak point in the circuits of the prior art, under these conditions, is the lower switch which should maintain an open circuit in steady state. The lower switch will conduct undesired current when the voltage across its terminals exceeds the device breakdown voltage (BVCEO for bipolar junction transistors). This weakness is directly related to the peak head voltage swing, as the voltage across the open lower switch is equal to the voltage across the head inductor and the closed lower switch during peak swing. For example, in the circuit of FIG. 2B:
VCCxe2x88x92(VSD+VR231)=VCE,off less than BVCEO (steady state)
which provides,
xe2x80x83Vh(peak)+VCE,min=VCE,off less than BVCEO (in transition)
Vh(peak) less than BVCEOxe2x88x92VCE,min
For BVCEO around 5.5 volts, this provides for a maximum allowable VCC of slightly more than 5.5 volts, and a maximum achievable Vh(peak) of slightly less than 5.5 volts.
A second point of weakness in the circuits of the prior art is the open-circuit upper switch during transition. For the circuit of FIG. 1B:
Vh(peak)+VBE,on=VCE,off less than BVCEO
Vh(peak) less than BVCEOxe2x88x92VBE,on
which provides for a maximum head voltage swing near 4.8 volts for BVCEO≈5.5 volts and VBE,on≈0.7 volts. The loss in maximum swing caused by the base-emitter voltage VBE,on can be reduced by using FETs as shown in FIG. 2B. The FETs have a gate-drain maximum voltage VGD,max, as well as a gate-source maximum voltage VGS,max, beyond which the performance of the FET devices is no longer reliable. In a five volt BiCMOS process, these process determined maximum voltages can be in the range of 5.5 volts. For the circuit of FIG. 2B:
Vh(peak)+VSD,on=VSD,off less than VGD,max
Vh(peak) less than VGD,maxVSD,on
which provides for a maximum head voltage swing near 5.5 volts for VGD,max≈5.5 volts. This head swing limitation illustrates an undesired design limitation in the circuits of the prior art.
The present invention is a cascode H-bridge circuit with particular application to magnetic recording write driver circuits. The present invention avoids the process dependent limitations placed on the head voltage swing in the H-bridge circuits of the prior art. Whereas the circuits of the prior art attempt to increase head voltage swing by minimizing device voltage drops in the current path, the present invention inserts cascode transistors in the current path that have less than a one-volt voltage drop when active, yet allow the circuit to operate under a higher voltage supply with roughly twice the head voltage swing available in the same process in the prior art. By implementing a cascode configuration, the present invention is able to support head voltage swings in excess of the switch breakdown voltage (BVCEO) without failure of the switches in the xe2x80x9coffxe2x80x9d state.
In the preferred embodiment of the present invention, cascode transistors are coupled between each switch and the inductive load. The cascode transistors are coupled and biased to switch off automatically when required to provide cumulative protection against device breakdown. In this manner, the cascode transistors are self-switching. The cascode transistor and the corresponding switch transistor combine to form a cascode switching element. Upper FET cascode transistors are biased to be conducting when the voltage across the transistor is in the safe range of the upper switch. When the voltage across the FET cascode transistor becomes large, as when the inductor terminal experiences a voltage spike, the FET cascode transistor turns off, combining its maximum allowable voltage with that of the original upper switch to provide twice the reliability protection of prior art circuits. Lower cascode Schottky transistors are base-coupled through resistors to a second bias voltage. The resistors enable the collector and emitter voltages of the cascode transistor to flex downwards with sharp downward voltage spikes to provide good compliance, i.e. maximum voltage range. When the lower switches are turned off, the associated cascode device shuts off due to lack of current. When shut off, the lower cascode Schottky transistor and the lower switch provide a breakdown voltage rating twice as large as the prior art. Both traditional and current mirror-based H-bridge implementations are provided.